Formal Verification of Divider Circuits by Hardware Reduction
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski · 2023
The paper introduces a novel verification method of gate-level hardware implementation of divider circuits. The method, called hardware reduction, accomplishes the verification by appending the divider circuit with another circuit, which implements its arithmetic inverse, followed by logic synthesis. If the circuit under verification is correct, the resulting resynthesized circuit becomes trivially redundant (composed of wires or buffers only). This method outperforms the established Boolean satisfiability, SAT-based and equivalence checking techniques and does not require a reference design.