GPPU: A 330.4-μJ/ task Neural Path Planning Processor with Hybrid GNN Acceleration for Autonomous 3D Navigation
Seokchan Song, Donghyeon Han, Sangjin Kim, Sangyeob Kim, Gwangtae Park, Hoi‐Jun Yoo · 2023
A graph neural network (GNN)-based neural path planning processor, GPPU, is proposed for 3D navigation on mobile platforms. It realizes high-speed and energy-efficient path planning by using the hierarchical path planning (HPP) with three key features: 1) graph generation core (GGC) with structured dynamic resolution sampling (SDRS) and K-NN node grouping (KNG) block for GNN preprocessing, 2) reordered grid prefetcher (RGP) and hybrid diagonal-densedistributed matrix $(\mathrm{D}^{3}\mathrm{M})$ aggregation architecture for fast and efficient GNN acceleration, 3) low-latency core cluster using GNN layer fusion (GLF) for external memory access (EMA) reduction. The GPPU is fabricated in a 28 nm CMOS process and successfully demonstrates in the 3D path planning application with 1.79 ms latency and $330.4 \mu \mathrm{J} /$ task energy efficiency at 0.9 V, 200 MHz operation condition.