A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations
Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim · 2023
This work presents a bit-serial computing hardware accelerator with a $20 \times 10$ fully-parallel processing element (PE) array for solving one-/two-dimensional (1D/2D) coupled partial differential equations (PDEs) with key highlights, including reconfigurability, scalable PE architecture with minimal energy/area overhead, and high parallelism. The test chip is fabricated with a 65nm technology, occupying a core area of 0.458mm2and consuming 107.8pJ and 110.8pJ, respectively, for solving 1D and 2D coupled PDEs at 1V and 25.6MHz.