CSA Based Radix-4 Gemmini Systolic Array for Machine Learning Applications
Muhammad Akmal Shafique, Kashif Inayat, Jeong–A Lee · 2023
Systolic arrays are becoming the backbone of machine learning accelerators due to high computational parallelism and data re-usability. This paper presents a novel fully factored systolic array architecture: it extracts out the booth encoding logic which is common across rows and carry propagate adder which is common across columns of the array. It results in significant reduction in area, power and delay. We have demonstrated the proposed scheme in open source Gemmini systolic array. The proposed systolic array fully integrates into the Gemmini accelerator without effecting it’s functionality. The proposed systolic array architecture achieves up to 54%, 8.9% and 42.5% reduction in area, delay and power respectively, as compared to baseline Gemmini systolic array. The ADP and PDP of the proposed SA improves by 58.2% and 47.6% respectively.