A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing
Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck · 2023
We present a flexible and scalable FPGA overlay architecture for data-flow applications. The overlay consists of a 2D grid of tiles consisting of compute units that can be exchanged at runtime. The overlay can deal with unbalanced data-flow graphs and is based on AXI-Stream to facilitate extensibility using IP and High-Level Synthesis. To support compute units that also require random access to the system memory, AXI4-ports can be enabled per tile at design-time. We implement a prototype of the overlay architecture tailored to the application domain of analytical query processing on a Xilinx Alveo U280 board. In this system, an overlay grid of$11\times 4$compute unit tiles occupies one-third of the available resources. with a design I/O throughput of$11\times 3.75\ \text{GB}/\mathrm{s}$. The overlay and HLS-based SIMD compute units provide full-throughput data processing, but are limited by the memory subsystem implemented with vendor IPs.