b8c: SpMV accelerator implementation leveraging high memory bandwidth
José Oliver, Carlos Álvarez, Teresa Cervero, Xavier Martorell, John D. Davis, Eduard Ayguadé · 2023
Sparse Matrix-Vector multiplication (SpMV), computing$y=A\times x$where$y, x$are dense vectors and$A$is a sparse matrix, is a key kernel in many HPC applications. Vitis Sparse Library's double precision SpMV (VSpMV) [1] is, to the best of our knowledge, the only performance-oriented, double-precision (64-bit) floating point implementation of SpMV on FPGAs equipped with High Bandwidth Memory (HBM).