Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management
Antonio Filgueras, Miquel Vidal, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell · 2023
In state-of-the-art FPGA, especially in chiplet-based devices, place and route has become an important challenge due to an increase in device size and complexity. In the same way, off-chip memory resources have grown in size and number of memory modules. Making efficient use of them has become a difficult task.