From Acceleration to Accelerating Acceleration: Modernizing the Accelerator Landscape using High-Level Synthesis
Rishov Sarkar, Cong Hao · 2023
The field of machine learning continues to grow at an exponential rate. As conventional CPU and GPU architectures struggle to keep up with demands of real-time performance, energy efficiency, and high throughput, researchers are increasingly turning towards FPGA acceleration to solve these challenges through customized computing architectures. Recently, High-Level Synthesis (HLS) tools have emerged, aiming to bring the ease of C/C++ software development to FPGA and ASIC hardware acceleration through an automatic conversion process (“synthesis”) to RTL code. However, HLS still remains far from the level of accessibility achieved by software design, retaining most of the challenges of traditional RTL-based hardware design. For instance: