FPGA implementation of Parameterizable Pattern-generator Modules for LBIST applications
K. Siva Sankar, R S Geethu, Ramesh Bhakthavatchalu · 2023
In this paper, a parameterizable Linear Feedback Shift Register design for LBIST applications is designed and implemented in Basys-3 FPGA board using Xilinx Vivado Suite 2020.1. The LFSR mainly helps us in pseudorandom test vector generation which can be used in Pseudo Random Pattern Generator (PRPG) and Multiple Input Signature Register (MISR) units for Logic Built In Self-Test (LBIST) applications. Increasing complexity and usage of Integrated Chips in military, medical, automobile and satellite devices has paved in the way for industries to look into LBIST based on-site chip testing instead of old traditional ATE based testing where the device had to be taken to ATE based test centres for probing, testing and validations. The design proposed in this paper can be reconfigured into multiple configurations like internal, external and complete configurations. Proposed design can also be programmed into multiple polynomial configurations based on intended application. Reconfigurable LFSR configuration features also integrated in the proposed design helping users to test the majority of the random pattern resistant faults present in the circuit while utilising the LFSR to create more sequences without increasing storage needs. The proposed design can generate multiple range of bits based on its intended applications.