Implementation of Table-Based Cyclic Redundancy Check (CRC-32) for Gigabit Ethernet Applications
P. Kishore, Bolli Abhinay Pal, Lolakapuri Nanda Kishore, Chintamreddy Venkata Revathi · 2023
As the transaction data is Over 2.5 quintillion bytes per day. To transmit data between datacenters, Ethernet networks requires high speed and fast error detection techniques. High performance CRC-32 (Cyclic redundancy check) parallel architecture for Gigabit ethernet application is proposed in this work. This is a table-based approach. This is designed based on highly parallel algorithm. In this work a generating polynomial with hex value (04C11DB7) is used for generating CRC-32 value. According to this architecture a data frame’s CRC value is calculated in a divide and conquer fashion. In this work 128 bits are used as input to CRC module and respective CRC value is calculated. This architecture processes 128 bits per second. Look tables are utilized for this purpose. Around 16 lookup tables are used for this purpose. This algorithm can achieve throughput of 10 Gbps for a clock input of 83.33Mhzs speed. Higher speeds can be achieved by increasing clock speed. Further throughput can be increased by increasing number of bits processing for second. This architecture is compatible for any size of data input, but it processes 128 bits per second. 256x32 bit size of SRAM is used to store content of look up table. About 16kb SRAM is costs for storing all table contents. The proposed model is implemented in Verilog in Xilinx Vivado – 2022 tool. Further design can be extended to other CRC polynomials.