Using Gate Tunneling in Bulk CMOS to Create a PUF
Patrick Camilleri, Shahram Mossayebi, Kenneth G. Paterson, Charles Grover · IEEE Internet of Things Journal · 2023
Physically Unclonable Functions (PUFs) in silicon have received significant attention since their initial proposal, with a wide variety of different designs available. This is largely due to their ability to provide device-specific outputs which can be used in diverse applications such as authentication, attestation, and cryptographic key generation. Existing designs for silicon PUFs are based on exploiting manufacturing variation in delay lines or the behaviour of memory cells to provide device-unique outputs. This paper proposes a new kind of PUF which we refer to as a Gate Tunnelling PUF. Our PUF design exploits the effect of manufacturing variation on quantum gate tunnelling current to generate unique, reproducible, yet unpredictable PUF outputs. A significant benefit of our design is its realisability in standard CMOS technology, leading to easy integration of our Gate Tunnelling PUF with other security and general system functions in single-chip designs. We have prototyped our Gate Tunnelling PUF design, producing test devices in arrays of 3584 output bits. Initial results are very promising, showing good randomness, uniqueness, reproducibility and temperature stability. These properties suggest that our devices’ outputs require minimal post-processing to be used for cryptographic keys.