An Indigenous 32 Bit Pipelined Processor for Space Applications
Nimmy Joseph, Joji Daniel, K Padmakumar, Anna Priya Koshy · 2023
In this paper, we present an indigenous 32-bit five stage pipelined processor designed and developed for future ISRO missions. The processor is a RISC processor based on IEEE 1754 instruction set architecture. It has a IEEE 754 compliant floating point unit, 1553B bus protocol controllers, timers, precise trap handler and internal memory. The processor is fabricated in 180 nm CMOS technology at Semiconductor Laboratory, Chandigarh at a frequency of 210 MHz external clock.