An Improved switching activity optimised LFSR for energy efficient BIST applications
Orugonda Naga Damini, S. Nagaraj, Chilakapati Sripriya, Sirisha Senthil · 2023
Since many years, BIST has used (LFSRs) linear feedback shift registers to generate test patterns; nevertheless, a recent issue with design limitations has caused significant advancements in this area. In order to create test patterns for a given primitive polynomial LFSR TPG, this study provides a switching activity optimised bit swapping LFSR technique. In this case, LFSR test patterns are transformed into numerous test patterns. Moreover, to support updated Multiple Input Signature Register testing that includes expanded output response analyses. In the LFSR generation phase, reconfigurable LFSR with better reseeding is used to broaden fault coverage. The length of TPG can be changed using parametric initialization to allow a wide variety of CUTs. The BS-LFSR is coupled with a modified MISR to reduce the peak and average power (scan and capture) during the test cycle or in response to a signature analyzer. These methods significantly reduce the peak testing power while improving fault coverage or testing time.