Power Evaluation of MIPS Architecture using Clock Gating Technique on FPGAs
V Prasanth, K. Babulu, Maddu Kamaraju · International Journal of VLSI Design & Communication Systems · 2023
The demand for energy-efficient computing systems has grown exponentially in recent years due to the increasing reliance on electronic devices and the escalating concerns over power consumption. In this paper, we present a comprehensive study on the power evaluation of MIPS (Microprocessor without Interlocked Pipeline Stages) architecture by leveraging power reduction techniques on FPGA (FieldProgrammable Gate Array). Various FPGAs are evaluated for their power characteristics when employing clock gating at different levels of the MIPS architecture. The work assesses the impact of clock gating on power consumption, performance, and area utilization across a range of FPGA platforms. Results indicate significant reductions in power consumption with minimal impact on performance, demonstrating the potential of clock gating as an effective power optimization technique in FPGA-based implementations of MIPS architecture.