An Application-Oriented Approach to Designing Hybrid CPU Architectures
Anna Yue, Sanyam Mehta · 2023
Hybrid CPUs have recently launched in desktop and laptop devices with the goal of increasing core count at manageable power consumption. These CPUs contain ‘performance’ and ‘efficiency’ cores, with a dedicated scheduler to assign tasks to cores. We find that these cores are not well-suited for any specific class of applications, and the efficiency cores are often smaller versions of the performance cores. This reduces the efficacy of scheduling tasks to cores. We show that instructions per cycle (IPC) per core serves as a natural metric to divide applications into two distinct classes. We use this division to propose a ‘mountain’ core with large core structures and a lower dispatch/retire width and decreased execution units (and thus lower number of ports) for low IPC applications, and a ‘plateau’ core with small core structures and increased dispatch width and execution units for high IPC applications. These changes tailor the hybrid CPU to the applications being run, allowing us to improve in both power and performance. We find that when compared to a Goldencovelike performance core, the plateau core on average improves performance by 8%, performance per Watt by 14%, and ED2P by 25% for high IPC applications; the mountain core on average improves power by 30%, performance per Watt by 34%, and ED2P by 17% for low IPC applications.