An Efficient Design of FSM Based 32-Bit Unsigned Pipelined Multiplier Using Verilog HDL
Prasanna Mishra · Zenodo (CERN European Organization for Nuclear Research) · 2023
This paper shows a modification to FSM based 32-bit pipelined multiplier. It uses carry look ahead adders (CLA’s) and Carry Select Adders (CSA) in place of ripple carry adders (RCA’s) in 32-bit FSM based pipelined multiplier for reducing the carry propagation delay. The proposed hardware design is based on shift and add algorithm for multiplication process.