A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-nand Technology and Featuring a 23.3 Gb/mm 2 Bit Density
Ali Khakifirooz, Eduardo U. Anaya, Sriram Balasubrahmanyam, Geoff Bennett, Daniel Amaral de Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzmán, Chang Wan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, Owen W. Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala · IEEE Solid-State Circuits Letters · 2023
We present the industry’s first 5b/cell (PLC) NAND chip, fabricated in a 192-layer floating-gate (FG) technology. With a die capacity of 1.67 Tb and an area of 73.3 mm2, it delivers a record bit density of 23.3 Gb/mm2. Key innovations to enable reliable PLC operation and the features implemented to support system-level usage are described. These include: a fast soft-bit read algorithm capable of handling the presence of defective bitlines; a fast read-calibration algorithm; a reverse-read waveform to improve the read margin; SLC-write-through; and program suspend and resume algorithm compatible with the above read operations.