An Efficient Design and Performance Analysis of Novel 8 Bit Modified Wallace Multiplier Using Kogge-Stone Adder (KSA) in Comparison with Ripple carry adder (RCA)
K. Sathish, P Jagadeesh · 2023
Aim: This research presents the design and implementation of an 8-bit modified Wallace multiplier using the proposed Kogge-Stone Adder (KSA) and compares its performance with the Ripple carry adder (RCA). Materials and Methods: In this research, a VHDL implementation of an 8-bit modified Wallace multiplier based on the KSA and the RCA has been developed. Modelsim is used to simulate the design, and the results are compared with those of the RCA-based design. The study was able to visualise the waveforms produced by the multiplier and assess its effectiveness with the help of this programme. During the simulation, input data was collected and used to test the multiplier. Delay and power consumption were used as metrics for the multiplier's effectiveness. Twenty sample data sets were used in the study, with ten from each of two groups. The modified Wallace multiplier was applied to the KSA and the RCA, with each adder receiving the same number of samples. G-power was used to analyse the results, and alpha and beta were set at 0.05 and 0.20, respectively. The study used a 95% confidence interval for its findings. Result: The simulation results of the proposed 8-bit modified Wallace multiplier using the KSA showed a delay of 28.5 ns, which is significantly lower compared to the delay of 36.1 ns in the traditional RCA based design. The significance level of the study is p=0.578 which is (p>0.05). Conclusion: In conclusion, the delay of the proposed 8-bit modified Wallace multiplier based on the KSA is insignificantly lower than that of the conventional RCA-based version.