Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL
Rambabu Sanivarapu, Mallikarjuna Rao Y., C. Venkataiah, Linga Murthy M.K., Laith H. Jasim Alzubaidi, Vyeshikha · E3S Web of Conferences · 2023
Due to recent developments, the POSIT number system, winch has been planned as a successor for numbers that are expressed in IEEE floating-point, which are in the focus of advances in arithmetic. Although this format claims to deliver more precise outcomes with the same bit width as ordinary floating point, the duration of the operation fluctuation during posit field identification poses a hardware design problem. The POSIT-based MAC Unit is created using Verilog HDL in this study, and the designed architecture is evaluated for good operation before being implemented on an FPGA using Xilinx Vivado.