Low-power architectural design and implementation of reconfigurable data converters for biomedical application
P. Rama Krishna, T. Santosh Kumar, Sandhya Avasthi, Suman Lata Tripathi, Boppidi Srikanth, Kakarla Hari Kishore · 2023
This chapter presents a reconfigurable CMOS data converter that is intended for the evaluation of implanted bioimpedance monitoring devices including mixed-signal systems. Well with the aid of a unique switching network, it may be configured as an ADC & DAC. A low-power automated adaptation unit is developed and employed as a front-end component. The adaptation circuit might be responsible for configuring the sample rate as well as resolution of the output signal depending on the frequency and amplitude of the input signal, respectively. The converter operates in two modes, lower and higher resolution for 8-bit and 12-bit data, respectively. If the incoming signal frequency would be less than 50 kHz, then the sampling rate is usually kept low; whereas if the input frequency range is more than 50 kHz, its sampling rate is usually kept high. The converter supports bandwidths of up to 10 kHz with low-resolution mode and up to 1 GHz for high-resolution mode. We obtained reduced power consumption by combining the dynamic threshold metal oxide semiconductor (DTMOS) technology with an extreme low power comparator. All of the circuitry stated above has been created utilising CMOS technology. All the ADC and DAC clocks are designed on Cadence Virtuso version 6.5 at 180 nm technology node.