MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA
Shivani Shah, Nanditha Rao · 2023
Performance evaluation of caches is an important component of the design process. Software or analytical model-based simulation approaches, although used by architects, are abstract models and are, therefore, not completely accurate. RTL-based simulators can be automatically mapped to FPGAs and can also be faster than software simulators. We present an FPGA accelerated multi-core cache simulator MCSim supporting a parameterized two-level cache structure. It can be partially reconfigured to include prefetchers and can simulate several cache configurations in parallel. We run a set of SPEC 2017 benchmarks on MCSim and find that it can run nearly 2.61x and 5.33x faster (on an average) as compared to ChampSim and Sniper for a 4-core framework, and 7x and 11.5x faster (on an average) as compared to ChampSim and Sniper in a single-core framework to generate hit/miss rates. We also present the scalability of our simulator on FPGAs with larger number of resources.