ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors
Qilin Si, Benjamin Carrión Schäfer · 2023
Application Specific Instruction Set Processor (ASIPs) have been proposed in the past to increase the performance while reducing the energy of general-purpose processors. These ASIPs are normally generated at the RT-Level (Verilog or VHDL). In this work we leverage the advantages of High-Level Synthesis (HLS) by designing the complete ASIP in ANSI-C. HLS is a single process synthesis method, thus, the key is to merge the CPU and hardware accelerator descriptions. This allows us proposed flow to synthesize the entire system together, which has numerous advantages like being able to reduce the total area, while further minimizing the power as the HLS process can now fully co-optimize the ASIP by e.g., maximizing resource sharing.