Implementation of Manifold Harassers to Aggravate Memory Failure Rate During Post-silicon Validation
G.C. Gagan, Shyam Kumar Parimi, Anil Bindu Lingambudi · 2022
Modern computing systems, from servers to mobile devices, expend significant time and energy in moving data between processors and memory [1]. Each of the design phases in the life of a SoC is equally important for the success of the product. In post-silicon validation, the main goal is to improve the quality and stability of the SoC (System on Chip) before release to market. As part of Memory Functional Validation (MFV), it is imperative to validate distinctive features of the Memory Controller (MC), check boot stability & system behavior under stressful workloads with multiple memory suppliers and capacity. This can be achieved by identifying, debugging, and root-cause hardware level bugs at the earliest. The chance of hitting a bug is proportional to the number of times the hardware flow occurred while test content is executing. In this paper, the proposed test flow increases the Hardware Flow Hit Rate (HFHR) and verifies the test intent. Harassers are configuration files which change the hardware configuration to stress/force the system to increase the specific HFHR and PMONs to verify the intent of the feature. Enhanced test flow consists of Harassers and Performance Monitors (PMONs). With harasser implementation enabled, an increase in hardware flow hit rate of ~4x is observed for Write mode and ~3x for Power-down test cases, during the SoC memory controller validation.