Novel, Clock Gating Broadcasting Applications for Low-Power FPGA Architectures
Tata Jagannadha Swamy, P. Vijay Kumar · 2023
In VLSI technology, clock gating strategies and designs are required for efficient power utilization as well as for other design applications. In this connection, clock is one of the efficient tools for Gating Broadcasting Applications for Low-Power FPGA Architectures. The proposed method mainly explores the use of clock gating strategies to reduce the power utilization for streamed applications that result from asynchronous dataflow architectures. Streaming applications include a wide variety of computer methods from diverse fields as digital logic, digital content coding, encryption, etc. The dynamically streaming nature of algorithms is taken into account in this research to present a set of strategies that can produce power usage by selectively shutting off sections of the circuitry when they are briefly dormant. These methods may be included into the synthesis phase of a high-level dataflow design flow without regard to the semantics of the program being designed. At scale implementations based on field-programmable gate array platforms show that power may be reduced without impacting bandwidth utilization, according to experimental studies.