High Speed Low Error Approximate Adder Using Hybrid Bit Truncation
Hema Chitra S, K. Kavya · Research Square · 2023
Abstract In Error Tolerant Applications (ETA) the compaction of energy consumption is done but the qual- ity of output is got rid by approximate addition. The ETA eases the strict accuracy restriction, and at the same time achieves tremendous improvements in both power consumption and speed performance. In existing approximate adders there are two types of truncation schemes such as zero-bit-truncation and non-zero-bit truncation. Truncation is applied to the LSB part of the data. Zero-bit-truncation is adding of zeros in the LSB part. Non-zero-bit-truncation is adding of constant ones in the LSB part. In this paper, the objective is to design a high-speed approximate adder using hybrid bit truncation approach. The proposed method is the com- bination of zero-bit truncation and the non- zero-bit truncation. The data is divided into equal lengths and unequal lengths padded with 10 and 01 combinations in the LSB part. Hybrid bit truncation is implemented us- ing ripple carry adder. The Proposed approach is simu- lated in Xilinx Vivado tool and implemented in Cadence Genus Compiler tool to obtain Area, Power, and Delay. The results are compared with non-zero- bit truncation method. Results shows that the hybrid bit truncation method has a reduction on area of 34.02%, power of 38.2% delay of 54.74% and the error metrics MED is reduced up to 70%.