DESIGN OF LOW POWER AND HIGH SPEED CMOS D-FLIPFLOP USING HYBRID LOW POWER TECHNIQUES
International Research Journal of Modernization in Engineering Technology and Science · 2023
This Paper details about the design of a Novel D Flip Flop (DFPFP).This D Flip Flop circuit is examined using supply voltage level techniques.The main purpose of these methods is to lower the power consumption caused by leakage currents.Also, the duration of battery backup and the supply power provided in standby mode are reduced as a result of the adopted technique.The proposed circuit employs fewer transistors, resulting in leakage currents and power consumption that are within acceptable bounds.Binary counters, shift registers, analogue, and digital circuit designs are among the main uses for CMOS D flip-flops.And the Cadence Virtuoso Tool uses 45nm CMOS technology to construct this circuit design.