A Novel Approach for Test Pattern Generation using ALU
K Kaarthik, C Vivek, Sivaranjani · 2023
The Ability to add increasingly complex functionality to an integrated circuit (IC) is made possible by its increasing capabilities. An example of common, the components included in an intricate circuit that will be utilized again as testing is the processor. It has been demonstrated that by looping arithmetic operations, processors can achieve fault coverage (FC) levels that are comparable to LFSR. To increase the fault coverage, weighted pseudorandom approaches have also been applied. Low power and testing time are the results of these weighted pseudorandom approaches. The ability to reuse arithmetic given data used internally for channels in order to test system cores making test vectors with arithmetic operations as an appealing approach. With an aim of sending the test vectors, there is no need for a dedicated bus or additional IC space; they can be transmitted to the Modules Under Test through normal address or data buses (MUT). The addition operation, which is typically executed with help of hardwarewhich is having additional energy and time efficient than the other three basic arithmetic operations, has the most advantages of all the ones that are present in processors. Additionally, the test vector perhaps divided into small- scale operations by generating the carry signal if the buses require that it be transmitted in parts. This Proposed work suggests a technique for creating a test pattern generator (TPG) that is both low power and area efficient. Instead of the binary adders used in the ALU, recently suggested Carry Select Adder is used over the design based on TPG. In comparison to older designs, this makes it possible to achieve low speed, low space, and low power consumption.