Security Implications of Decoupling Capacitors on Leakage Reduction in Hardware Masking
Soner Seçkiner, Selçuk Köse · 2023
Hardware masking is a countermeasure against side-channel attacks and aims to separate sensitive information to be processed into multiple shares. Ideally, a side-channel attack can be successful only if information from all of the hardware masking shares is available. Due to the non-ideal nature of practical VLSI implementations, the sensitive information from a share can, however, leak to the other shares, making side-channel attacks successful without collecting information from each share individually. Alternatively, the theoretical assumption of independence among hardware masking shares can be violated in practical implementations. The effectiveness of hardware masking decreases due to the parasitic impedance of power delivery networks. The noise propagation and coupling among hardware masking shares that are powered through the same power delivery network leads to a successful side-channel attack with less number of measurements. The implications of the size and placement of on-chip decoupling capacitors on noise coupling among hardware shares and effectiveness of hardware masking is investigated in this paper. The simulation results demonstrate that the t-test value can be as low as 1.62 with distributed decoupling capacitors, where a circuit with a t-test value below 4.5 is typically considered secure.