FPGA Based Area Reduction with Recurrent Neural Network and VHDL Modelling
Smita C. Chetti, Shilpa Patil, Ramya HR, Gandla Shivakanth, K. S. Shashidhara · 2023
While Field Programmable Gate Arrays (FPGAs) and other forms of reconfigurable hardware have been available to designers for the better part of the past three decades, many implementations still fail to take use of the devices' full potential. Systems that execute partial runtime reconfiguration of the device have the potential to make more efficient use of available resources if they are designed and implemented early in the process. The speed and size of reconfigurable FPGA fabric have increased in recent years as the number of complex parallel programmes that may be run on a single device has increased. It has never been possible to acquire such skill. Each time a device performs a partial reconfiguration of a segment of the fabric, the system's operation is disturbed since it is unable to get access to the resource. This means that when the device is redesigned, more of the available reconfigurable resource will become accessible. The fundamental goal of this thesis is to increase the efficiency and reduce the power consumption of run-time digital systems that rely on dynamic partial reconfiguration, all without sacrificing the functionality of these systems (DPR). The idea enabled two major advances. The first positive step towards the desired reconfigurable system was made when a method was established for building the programmable logic reprogramming array using Recurrent Neural Network (RNN). An FPGA's main purpose is to reprogram the interconnects of an array system, in addition to programming logic blocks. DPR was designed to be as efficient as possible in terms of both power consumption and physical footprint so that the cognitive system could be managed and accessed in real time. Its setup, design flow, and portability are only a few of the metrics used to evaluate the system's overall efficacy. In compared to a full reconfiguration, it requires less time, space, and power to get the job done. Our success may be attributed to our use of the Cadence-CMOS technology's built-in apk 45 nm library functionalities.