Design and Implementation of RNB multiplier Using NP Domino logic
Bhavana Majji, K. Ragini · 2022
In this paper, a Reordered Normal Basis (RNB) finite field multiplier is implemented using NP domino logic. This multiplier uses RNB, which is the type-II Optimal Normal Basis (ONB), to perform multiplication. The Critical Path Delay (CPD) is influenced by the XOR-AND-XOR (XAX) module of the Serial-In Parallel-Out (SIPO) RNB multiplier. Hence, this block is designed in various logic styles, including, static CMOS logic, pseudo NMOS logic, domino logic, domino keeper logic, and NP domino logic. The Tanner EDA 45nm tool is used to design the multiplier using the full-custom design. The major goal is to determine the optimum logic style that meets the VLSI optimisation requirements like the area, multiplication delay, CPD, power dissipation, Area-Delay Product (APD), and Power-Delay Product (PDP). When compared to other logic styles, the delay and area of the multiplier employing NP domino logic are lower, whereas the power dissipation is similar to other domino logic styles. Also, the architectures of Serial-In Serial-Out (SISO), Parallel-In Serial-Out (PISO), SIPO, and Parallel-In Parallel-Out (PIPO) multipliers were implemented to analyse their efficiencies in terms of design parameters.