Efficiency Analysis of Concurrent Error-Detection Circuits on the Basis of Assessment by Belonging of Calculated Functions to Self-Dual Class and Preliminary Compression of Signals Using Linear Codes
D. V. Efanov, Tatiana S. Pogodina · PROGRAMMNAYA INGENERIA · 2023
A method is described for checking of calculations on whether functions belong to the class of self-dual with using well-known linear codes for preliminary compression of signals from the outputs of combinational devices in order to reduce the number of controlled signals. A generalized structure for organizing the checking of calculations with signal compression using arbitrary separable codes is proposed, which complements the well-known structures of self-dual check of parity calculations («self-dual parity») and self-dual check with duplication of each function («self-dual duplication))). In the concurrent error-detection circuit according to the presented method, all devices, except for the self-dual complement block, are standardized (typical). Therefore, to synthesize the concurrent error-detection circuit, it is necessary to obtain only the structure of this block in the selected elemental basis. The article presents a technique for synthesizing a block of self-dual complement when organizing the checking of calculations using arbitrary separable codes. Examples of the implementation of devices with concurrent error-detection circuits based on well-known linear codes — parity codes, Hamming codes and their modifications are given. Some results of modeling devices with concurrent error-detection circuits are given, noting the advantages and disadvantages of using each of the codes considered. The results obtained in the study can be applied in the development of self-checking computing devices and systems.