Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension
Yao-Ming Kuo, Mark F. Flanagan, Francisco García-Herrero, Óscar Ruano, Juan Antonio Maestro · IEEE Transactions on Aerospace and Electronic Systems · 2023
The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem (BCH) and binary low-density parity-check (LDPC) codes. Despite the high error-correction capacity of non-binary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this paper, the feasibility of NB-LDPC coding for space telecommand link applications using a RISC-V soft-core processor plus a vector co-processor is demonstrated. The purpose of this work is to avoid the need for a dedicated decoder hardware, and thus the customized general-purpose processor which performs decoding can be reconfigured to perform other important on-board tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the on-board processor. The method of acceleration of a NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kbps is achieved for the Forward-Backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by CCSDS.