Lightweight and Efficient Hardware Implementation for Saber Using NTT Multiplication
Tianyu Xu, Yijun Cui, Dongsheng Liu, Chenghua Wang, Weiqiang Liu · 2022
Although Saber is no longer a candidate in the fourth round of the National Institute of Standards and Technology (NIST) just-announced post-quantum cryptography standardization process, Saber's lightweight and high-speed hardware implementation is still research interest and could be applied to digital signatures. During the process of encryption and decryption, polynomial multiplication is the most time-consuming and resource-consuming unit. Most of the previous research used Toom-cook or Karatsuba multiplication. In this paper, we use the saber-unfriendly but fast NTT multiplication, and a switchable butterfly computing unit is used in the polynomial multiplication process to improve speed and reduce the number of registers. The proposed design provides a good balance between frequency and area consumption which only uses 2247 LUTs, 327 FFs, and 6 DSPs and is capable of high clock frequency on FPGAs by 327MHz.