Design of 64-bit Floating-Point Arithmetic and Logical Complex Operation for High-Speed Processing
Bhuvana Suganthi D, M. Shivaramaiah, A. Punitha, M. K. Vidhyalakshmi, S. Thaiyalnayaki · 2023
The hardware floating point arithmetic units are needed for the scientific operations and high-speed data signal processing. This paper proposes very high speed floating point arithmetic unit for all complex data with the size of 64 bits and due to pipelining concept, the performance in the speed is improved for all the arithmetic and logical operations The reason of considering floating point numbers is good in resolution, higher dynamic range, no scaling needed and accuracy which is more attracted for complicated problems compared to fixed point though it has higher speed and lower cost characteristics. Single and double precision IEEE 754 standard are used to perform the required calculations and implemented using Verilog HDL and each module functionality is tested using test vectors. This method of approach for computing complex numbers with double precision floating point unit. The results on this proposed system are obtained in the parameters like delay, area and memory and proves of high efficiency and reduces critical path delay. This floating-point complex algorithm is simulated using Modelsim 6.4c, Xilinx tool is used to synthesize and executed in FPGA Spartan 3 XC3S 200 TQ-144.