Novel 32nm CMOS Ternary Parity Generator-Checker
Samanwita Mondal, Saptaparna Ghosh, Aditi Singha Mahapatra, Deblina Roy, Prerona Sanyal, Aloke Saha · 2022
Present study explores a new circuit topology for parity-based error detection in ternary domain. Proposed concept is discussed and applied to construct 4-trit Ternary even as well as odd parity generator-checker using conventional Enhancement-type Metal Oxide Semiconductor (MOS) transistor. Proposed idea adds two more redundant trit with the original ternary input sequence (i.e., one is for trit “1” and another is for trit “2”) to generate/check corresponding parity output. The complete circuit is designed on 32nm standard CMOS technology considering BSIM4 device model parameters with 1.0V supply rail at 27°C temperature. The ternary digits “0”, “1” and “2” are represented with 0V, 0.5V and 1.0V respectively. The extensive T-Spice transient simulations with all possible test patterns validate the proposed design. Ternary input for the simulation is applied using Piece-Wise-Linear (PWL) input source. Circuit speed-power response is evaluated and recorded.