Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADC
Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi · 2023
This work discusses a design methodology to unify fundamental security primitives, physically unclonable function (PUF), and true random number generator (TRNG) within the same circuit. Specifically, a case study is presented for analog circuits. By sharing and unifying the physical resources for many security modules, our methodology's integrated countermeasures' overheads are dramatically reduced, allowing robust security protocols even within limited area/power-starved edge nodes. Using successive approximation register (SAR) ADC as a test unit, we discuss how the capacitive array of the circuit can facilitate fingerprinting signatures for PUF and rich, dynamic entropy sources for TRNG. Our proposed designs are analyzed under various challenging scenarios, such as power supply variations and spatial correlations in capacitor arrays from where PUF/TRNG signatures are harvested. Even under dramatic variations, the proposed integrated security primitives' resiliency is maintained. Our intrinsically-designed PUF operates with ~5x lower energy. We discuss various design considerations to optimize the intrinsically designed PUF and TRNG performance.