Efficient MBIST Area and Test Time Estimator Using Machine Learning Technique
Darakshan Jamal, Ratheesh Thekke Veetil · 2023
In any SoC, 5-15% of the die area is consumed by Design for Test (DFT) logic to screen the manufacturing defect. This results in significant per part cost for test purpose. Approximately 65% of the DFT area is occupied by the memory test related logic. This means that average 6.5 mm2 of silicon area is dedicated for Memory Built-in Self-Test (MBIST) in 100mm2 die. In latest technologies, approximately $0.07-$0.15 is per mm2 die area cost. Hence significant amount of chip cost is consumed by MBIST logic. This shows that, there is a great opportunity to increase the profit margin (huge dollar saving in millions of units) by reducing the MBIST area. Area optimization may have adverse effect on test time. There is a requirement to balance MBIST area and test time to get optimal DFT area for SOC. To arrive at the optimum MBIST area and test time, different memory grouping and associated physical design challenges for routing and timing closure to be explored. This is a very time-consuming task as RTL generation to backend feedback typically takes several weeks. Multiple iteration during the project execution with different MBIST grouping is practically not possible due to resource and schedule constraints. In this paper, we studied different ML algorithms and propose the best suitable model for early estimation of MBIST area and test time without RTL generation and synthesis. Accurate estimation of MBIST area and test time is the primary step to arrive the optimum MBIST design to achieve higher profit margin by reducing area and test time.