Execution of Convolution Coding Method for FPGA in Industrial Automation using VERILOG HDL
Kanagaraj Venusamy, S. Kannadhasan, A. Vimalesh, Pradeep Chandramohan, M Shanmugam, K. Priyadarsini · 2023
In this paper, the performance study of the FPGA-based encoder is delivered and received with little errors given the large number of applications that employ digital communication to store and retrieve data recently. Forward Error Correction units a wireless communication system region that is essential. Several types of encryption methods have been measured, and the error is completely different Convolution code writing approach, an honest technique used to rectify mistakes during the data transfer. Convolutional encoder area unit compelled to provide the output in the kind of register style with specified positions in the register. The areas in which the region is entirely arranged are likewise shown as arrows. The position of the registers provides probable state transitions wherein example, L is the register's length. Using these facts, the best way to execute of data transmission in digital communication channels is to correct errors in codes. FPGA device utilized in convolutional encoder's hardware implementation. Vivado and XILINX ISE are used for performance analysis.