HCER: A High Cost-Effectiveness Multi-Bit Fault-Tolerant NoC Router
Wencai Gao, Xiaowen Chen, Chen Li, Jianzhuang Lu, Hanyan Liu · 2022
Networks-on-Chip (NoC) is quickly becoming the standard communication paradigm for the growing number of cores on the chip. The error correction code (ECC) is widely adopted in error correction NoCs to ensure that the data is correct. As the probability of multiple errors gradually increases, the trade-off between fault-tolerance and overhead requires careful consideration by designers. Therefore, this paper aims to improve the cost-effectiveness rather than just error correction capability. We propose HCER, a high cost-effectiveness multi-bit fault-tolerant NoC router. We first propose a speculative router architecture, which reduces the performance loss introduced by ECC. Secondly, we use 2D code instead of the traditional BCH code for multi-bit error-tolerant design, enhancing the error correction capability. As a result, our design could achieve a 16x improvement in cost-effectiveness over the baseline design under synthetic patterns and the PARSEC benchmark when under the same error correction capability. In addition, our router does not introduce large hardware overheads.