Adjustable Key AES Encryption and Decryption Circuit
Peiqin Jiang, Shuxiang Song, Mingcan Cen, Chaobo Cai · 2022
In this paper, an adjustable key AES encryption and decryption circuit is designed by applying iterative architecture techniques to address the problem that the Advanced Encryption Standard (AES) hardware design needs to occupy a large number of hardware resources. The circuit is compatible with three different encryption and decryption modes, AES-128, AES-192, and AES-256, and the user can select the encryption and decryption mode of the data according to his needs. Based on iterative architecture, the design uses a state machine to control the number of AES encryption and decryption round conversions according to different key lengths, while controlling the adjustable key extension module to expand the key internally and provide subkeys for the round conversions. During the wheel transformation, resources are shared between some of the common circuits of the decryption and encryption logic to reduce the overall resource consumption of the circuit. The designed circuit is based on the XC7VX485TFFG1157 comprehensive simulation from Xinlinx and consumes 1349 Slices, and 4700 Slices LUT, which can meet the requirements of wireless mobile networks and other resource-constrained environments.