28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $\mathsf{i}$
Bvunarvul Kim, Seungpil Lee, Beomseok Hah, Kanawoo Park, Yongsoon Park, Kangwook Jo, Yujong Noh, Hyeoncheon Seol, Hyunsoo Lee, Jaehyeon Shin, Seongjin Choi, Youngdon Jung, Sungho Ahn, Yong-Hun Park, Sujeong Oh, Myung‐Su Kim, Seonauk Kim, Hyunwook Park, Tae-Ho Lee, Haeun Won · 2023
As data produced by multimedia explodes and demand for data storage increases, the most important topics for the NAND-Flash memory field are continuous performance improvements and cost/bit reduction. To improve performance, features to improve the quality of service (QoS) as well as the read/write performance [1] are required. To reduce the cost/bit, the number of stacked layers needs to increase, while the pitch between stacked layers decreases. It is necessary to manage the increasing WL resistance produced by a decreased stack pitch. To overcome these challenges, this paper presents techniques applied to a >300-layer 1Tb 3b/cell (TLC) 3D-NAND Flash memory: 1) A tripleverify program (TPGM) technique is used to improve program performance. 2) An adaptive unselected string pre-charge (AUSP) technique is used to reduce disturb and program time$(\mathsf{t}_{\mathsf{PROG}})$. 3) A programmed dummy string (PDS) technique is used to reduce WL settling time. 4) An all-pass rising (APR) technique is used to reduce the read time$(\mathsf{t}_{\mathsf{R}}), 5)$A plane-level read retry (PLRR) technique is used during erase to improve the QoS.