Optimized Design Implementation and Research of SM3 Hash Algorithm Based on FPGA
Yingpeng Xu, Lin Han, Zhe Yu, Fang Che · 2022
With the further development of computer technology and the advent of big data in the 5G era, the demand for the design implementation of hash algorithms in high-performance hardware is increasing. The commonly used international hash algorithm standards are SHA-1, SHA-2, and SHA-3 series algorithms published by NIST, SM3 algorithm is the first national hash algorithm standard independently developed by China, and the high-performance implementation of the SM3 algorithm is part of China's move to the world. This paper proposes a two-in-one SM3 algorithm IP core implementation framework for the SM3 hash algorithm. For the compressed iterative part of the core operation of the SM3 algorithm, the framework uses a circular, iterative extension approach, adding registers to the combinatorial logic to implement a pipeline design. Moreover, the parallelism of hardware is used to improve the addition circuit and reduce the time delay of the longest critical path. The method uses a Virtex-5 FPGA device as the target device, and the SM3 algorithm achieves a maximum throughput rate of 1939.4 Mbps.