RepCut: Superlinear Parallel RTL Simulation with Replication-Aided Partitioning
Haoyuan Wang, Scott Beamer · 2023
Register transfer level (RTL) simulation is an invaluable tool for developing, debugging, verifying, and validating hardware designs. Despite the parallel nature of hardware, existing parallel RTL simulators yield speedups unattractive for practical application due to high communication and synchronization costs incurred by typical circuit topologies.