Performance Analysis of RNS Arithmetic Operations using Reversible Logic
Sunita Shirahatti, Rajashekar B. Shettar, Rohini Hongal, Uma Malenahalli · 2022
The need for portable communication devices with high performance and low power has grown significantly in recent years. The proliferation of portable communication devices has raised the bar for system performance. The essential building blocks of every DSP system are the fundamental arithmetic units like adders and multipliers. The speed, power, and area performance of these blocks has an effect on the system as a whole. Arithmetic unit computation time can be lowered to improve system performance. Due to the concurrent computations performed by the Residue Number System (RNS), the circuits are faster and more suited for high-speed digital signal processing. Reversible logic (RL) is regarded as one of the power optimization strategies in low-power CMOS VLSI architecture. In this paper, Reversible logic is employed to implement basic operations such as addition multiplication, forward and reverse converter on RNS using three moduli set (5,3,2). All the implementations are done on Xillinx 14.7 platform. Results shows that forward converter uses 165 LUTs and operates at a lower frequency of 68MHz because of the accessibility to ROM. The reverse converter consumes more power 10.5mW compared to other circuits as it involves more of multiplication operations. The methodology applied can be used in power efficient DSP applications to achieve low power and high speed.