Hardware Performance of Complex Dot-Product Implementations
Linda S. DeBrunner, Victor DeBrunner · 2022
Dot-product computations are at the heart of most signal processing algorithms. Often, the distinction between computing the dot-products of complex numbers and the dotproducts of real numbers is not considered to be significant. We will compare the computation of a real valued dot-product to the computation of a complex valued dot-product with respect to space, time, and accuracy using Verilog/VHDL simulation tools. From these implementations, we draw conclusions with respect to the hardware implementation of the DFT and similar DSP algorithms. Based on our investigations, these ideas indicate that a complex DFT will require about 3.9 times the area of a natively real valued DFT.