Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, M. Khosravian G., Matthieu Moy, Gabriel Radanne, Pascal Raymond · 2023
We consider the verification of electrical properties of circuits to identify potential violations of electrical design rules, also called Electrical Rule Checking (ERC). We present a general approach based on Satisfiability Modulo Theory (SMT) to verify that these errors cannot occur in a given circuit. We claim that our approach is scalable and more precise than existing analyses, like voltage propagation. We applied these techniques to a specific type of errors, the missing level shifters. On an industrial case-study, our technique is able to flag 31 % of the warnings raised by the voltage propagation analysis as being false alarms.