Enabling High-Speed DDR5 Memory Technology in a Low-Cost 4-Layer Motherboard Stackup
Alvaro Camacho Mora, Fernando Rodriguez, Ranjul Balakrishnan · 2022 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI) · 2022
In the cost-sensitive Client Desktop domain, memory platform design and performance on a constrained low-cost 4-layer (4L) type 3 Stackup continue to be major challenges. While traditional memory technologies like DDR4 with lower data rates have been successfully productized, addition of new memory technologies such as DDR5 poses newer risks to enabling higher performance. This paper discusses an alternative solution while adhering to the same PCB 4L stack-up for motherboard (MB), with Dual-POOL (Planes On Outer Layers) routing that allows faster DDR frequencies when compared to legacy routed platforms.