FPL Demo: An FPGA-IP Prototype Chip for MEC devices
Morihiro Kuga, Masahiro Iida, Hideharu Amano · 2022
This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.