Automotive Multi-Chip System with Cache Coherent Interconnect for Pipelined Parallel Applications
Daecheol You, Jae Min Kim, Tae-Sung Kim, Junho Huh · 2023 IEEE International Conference on Consumer Electronics (ICCE) · 2023
Due to the ever increasing computing performance required by Autonomous Driving (AD), the AD systems of high-end vehicles are equipped with multiple automotive SoCs. For chip-to-chip interconnect interface, cache coherent interconnect interface can be a good candidate since it supports shared-memory system by providing a single globally shared address space. With shared-memory system, the entire system can be managed by a single OS or hypervisor. Applications also do not need explicit data transfer and synchronization through I/O devices to communicate across the chip. However, since the interconnect between chips takes much higher latency compared to on-chip interconnect, significant performance degradation can occur when a host chip accesses memory in a remote chip. This is a painful problem of cache coherent Non-Uniform Memory Access (cc-NUMA) systems. This paper proposes an effective cache coherent interconnect architecture and automotive application binding scheme for automotive cc-NUMA system. The experimental results show that the system performance is improved by 22 % on average with the proposed architecture.