Three - Operand Binary Addition Using Parallel Prefix Adders
Sneha Elsa Reji, Deepa Susan Jacob · 2022 IEEE 19th India Council International Conference (INDICON) · 2022
The field of cryptography has seen remarkable progress with the introduction of three operand binary adders in the applications of pseudo-random bit generators (PRBG). This is especially true in the case of Modified dual-CLCG (MDCLCG) being it the safest and most random PRBG method. Parallel prefix adders which are extensively used for fast binary addition can be extended towards the use in three operand binary adders hence making them much more efficient. In this paper, all the basic six topologies of Parallel Prefix Adders – Han Carlson, Kogg – Stone, Brent – Kung, Sklansky, Ladner - Fischer and Knowles adders are used within the four stage architecture of a multi - bit three operand adder. All the adder designs with the word sizes of 16, 32 and 64-bit have been simulated and implemented on Xilinx Vivado Design Suite 2020.2 using the programming language Verilog HDL The architecture of these three operand adders are prototyped on the commercially available Basys 3 Artix-7 FPGA Board for the on-chip functional verification. Further, all these designs are synthesized using Cadence tool with GPDK 45nm technology library for the purpose of comparing various adders with respect to performance parameters – area, delay and power for the different word sizes.